Verilog is an HDL -- hardware description language -- which is used by developers to describe hardware. Verilog's name is derived from the language's capability to both verify and log the development and implementation of electronics components. SystemVerilog is an extension of Verilog, and expands on the HDL's protocols. Because of their relationship, the two HDL's are very similar. However, there are some key factors that enable you to distinguish them from one another.
SystemVerilog seeks to focus the capabilities of Verilog and improve on the language's ability to verify IP-based computer chips. SystemVerilog expands on Verilog with the implementation of "C" computer language support, enabling developers to define the HDL's protocols in popular computer programming languages like C and C++.
Verilog was developed by Automated Integrated Design Systems in 1985. Nineteen years later, Accellera introduced SystemVerilog to extend Verilog's capabilities. Verilog started out as a private HDL, before being made public in 1980. After Verilog became a public HDL, Acellera was able to both expand the standard to SystemVerilog and maintain the orphaned Verilog HDL.
Object and Assertion-based Verification
Unlike Verilog, the SystemVerilog HDL contains both object-based and assertion-based verification. SystemVerilog can be used to make true/false-type assertions on commonly used test modules, which cuts some of the work out of implementing external test modules for the verification process.
Verilog is assigned the IEEE 1364 classification by the Institute of Electrical and Electronics Engineers, while SystemVerilog is labeled as IEEE 1800. The IEEE decides upon a set of standards, or specifications, that projects must meet in order to bear the "IEEE" label. The numerical labels help to distinguish Verilog and SystemVerilog from the IEEE's countless other standards and projects -- there are over 1,300 hardware and software protocols developed by the IEEE committee.