How to Generate a Pulse on Falling Edge Veralog

Verilog allows you to design and test circuits using a PC.

Verilog is a Hardware Descriptor Language, or HDL, and it is used to describe digital circuits using programming language semantics. You can use Verilog and common programming language control statements like “if” statements to generate events in a digital circuit. For example, you can create an electrical pulse on the falling edge of a clock signal. A clock signal is a train of square waves, where each square wave is generated many times per second. There are two sides to the square wave: the rising edge and the falling edge. You can trigger events on either edge.

Things You'll Need

• Verilog Integrated Development Environment (IDE), such as Altera Quartus II (see Resource for link)

Instructions

1. Open the Verilog IDE and create a new project by clicking “File,” then selecting “New Project Wizard.” A project creation window appears. Select a name and directory for this project. For example, you can name the project “pulse” and place it in the directory “C:\Verilog Projects.” Press the “Next” button to move through the rest of the pages, leaving all of the settings at their default. Press the “Finish” button to create the project.

2. Select “File,” then “New” to open a file creation window. Select “Verilog HDL File” and press the “OK” button to add a new Verilog file to the project. A blank Verilog file appears in the main text editor window.

3. Define a new “module” that has the same name as the project. This module will house all of the code for the pulse program. When you define a module, you can also define input and output parameters. The “pulse” module needs two parameters: a clock signal and an output for the generated pulse. Write the following to define the module with these parameters:

   module pulse(clock, pulse);

4. Define two signals: an input clock signal and an output pulse signal. The clock signal is used to trigger a pulse on its falling edge. The falling edge is where the clock signal transitions from a high value to a low value. In contrast, the rising edge is the where the clock signal transitions from a low value to a high value. The clock signal maintains the high signal for the same amount of time as a low signal, creating a pattern that looks like a train of boxes. You can define both signals with the following two statements:

   input clock;
   output pulse;

5. Write the following statement to perform a sequence of actions with each tick of the clock signal, triggering on the falling edge of the clock:

   always @(negedge clock)

6. Place a single bit onto the “pulse” output signal, like this:

   pulse <= 1’b1;

7. End the module with the following statement:

   endmodule

8. Compile and test your circuit by pressing the "Play" button located in the main toolbar of the Quartus II software. This circuit generates a pulse on the falling edge of the clock signal.

References

• University of Main Electrical and Computer Engineering Department: Quartus II Introduction Using Verilog Design
• Sutherland HDL: Verilog HDL Online Quick Reference Guide

Resources

• Altera: Quartus II Web Edition Software