How to Analyze Your System Verilog Assertions
Verilog is a programming language that describes digital hardware. Assertions are statements that define expected conditions within a program. In Verilog, assertions are used to define states that your circuit should encounter during normal operation. These assertions can be used to analyze the circuit for faults. Any programming errors can lead to a failed assertion, which helps you to trace a bug back to its root cause. You should add assertions to your Verilog program to help you debug the system, and as a tool to aid other programmers when they review your code.
Other People Are Reading
Things You'll Need
- Verilog Integrated Development Environment (IDE), such as Altera Quartus II (see Resources for link)
Instructions
-
-
1
Open the Verilog IDE by clicking on its icon. Create a new project by clicking “File,” then selecting “New Project Wizard.” A new project window appears. Select a name and directory for this project. Press the “Next” button to move through the rest of the pages, leaving all of the settings at their default. Press the “Finish” button to create the project.
-
2
Select “File,” then “New” to open a file creation window. Select “Verilog HDL File” and press the “OK” button to add a new Verilog file to the project. A blank Verilog file appears in the main text editor window.
-
-
3
Create a module named after the project. For example, if your project is named “Assertions,” you can write the following module definition:
module Assertions;
-
4
Declare two registers that hold values, named “A” and “B,” like this:
reg A, B;
-
5
Set the initial value for each register like this:
initial begin A = 0;
initial begin B = 1; -
6
Suppose you have an “if” statement that tests whether “A” does not equal “B.” At this point in the program, this should always be true, since “A” and “B” were just initialized at different values. This would be a great place to put an “assert” statement. Write the following “if” statement, followed by an “assert” statement:
if (A != B)
assert (A != B); -
7
Write a more verbose “assert” statement that prints out messages whenever an “assert” statement is processed. Replace the “assert (A != B);” statement with the following:
assert (A != B) $display (“Assertion passed. A does not equal B.”);
else $error (“Assertion failed. A equals B.”); -
8
Run the program by pressing the green “Play” button located on the top toolbar. The program should print out the following message: “Assertion passed. A does not equal B.” However, if some bug occurs that sets the value of “B” to zero, the assertion will fail and the error message “Assertion failed. A equals B.” will appear.
-
9
Use assertion messages to analyze the state of your program and verify all of your assumptions about the design. When an assertion fails repeatedly, there is a bug in the program that fails to meet your design criteria. You can work your way from the assertion backwards to the root cause of this bug.
-
1
