How to Lock a Pin in VHDL

VHDL stands for "VHSIC hardware description language." This programming language works with electronic design automation to set up integrated circuits, gate arrays and other systems. When you're working with a software package that uses VHDL in systems design, you can import VHDL files and then lock in the pins of the device you're analyzing to particular signals from the testing device.

Instructions

1. Import the VHDL file you want to work with. If sing ispLEVER, go to "Source" and then "Import." A dialog box will pop up, so you should choose the folder where your desired file is located. Click on "Open" and find your file inside. Choose "VHDL Module" when the "Import Source Type" dialog box appears, and then hit "OK."

2. Go to the dialog box that contains the sources you're using for your project. In ispLEVER, this will be under "Sources in Project." Find "Processes for Current Source" and double-click on "Constraint Editor."

3. Move your mouse to "Loc" in the toolbar in the Constraint window and click it. When the signal list dialog box pops up, connect the pin numbers to their assignments. When you have finished locking signals to their pins, you can click "OK" to save the configuration. Save all of these changes.

References

• XESS: Xilinx ISE 10 Tutorial
• LIU: Introduction to ispLEVER
• Xilinx: Virtex-5 FPGA User Guide