How to Reduce the Ringing on a CMOS Clock Signal

Severe ringing in CMOS must be reduced to avoid catastrophic failure in electronic systems,

Less than perfect pulses in clock signals cause electronic circuits to process information incorrectly that can result in catastrophic failures and intermittent circuit behavior. A periodic waveform overlayed on the clock pulse, referred to ringing, is one clock imperfection that electronic engineers must correct. Reducing the ringing can sometimes be easily fixed with the addition of a capacitor or a resistor in the circuit. Occasionally, ringing can only be fixed if the clock line circuit is completely redesigned.

Things You'll Need

• Variable resistors
• Variable capacitors
• Clock drivers
• Oscilloscope
• Circuit simulator

Instructions

1. Insert a variable resistor with a range from 0.1 to 50 ohms in the output signal wire path of the driver where the ringing occurs.

2. Insert a variable resistor with a range from 0.1 to 50 ohms into the input signal wire path of the circuit whose output is ringing.

3. Connect a variable capacitor with a range between 1 and 100 picofarads and a variable resistor with a range between 100,000 and 1,000,000 ohms. Connect in a series where the unconnected capacitor lead is connected to the ringing circuit node and the unconnected end of the resistor is connected to the power supply voltage.

4. Adjust the variable resistor values in the circuit so that they are in the middle of the total resistance range. Do the same for the variable capacitor.

5. Connect your oscilloscope lead to the ringing node and apply the power. Adjust the variable resistors and capacitors such that the ringing is minimized as displayed on the oscilloscope screen,

6. Monitor the supply current of the circuit and the rise and fall time of the clock signal. Readjust the variables resistors and capacitor so that ringing is minimized; supply current is minimized; and the rise and fall time of the clock signal is minimized or all of these circuit specifications are within your required circuit specifications.

7. Insert a clock buffer or driver in signal path of the ringing clock line such that the driver is an equal distance between the circuit the clock signal drives and the clock driver circuit. Readjust the values of the variable resistors and capacitor so that ringing, supply current, propagation delay times and rise and fall times are minimized. Continue to insert clock buffers into the clock line in order to optimize circuit performance further.

Tips & Warnings

• Ringing on CMOS clock lines are often a result of improper circuit design and a lack of thorough circuit simulation. Simulate the clock line and the driver and receiver circuits on a circuit simulator such as SPICE. Include in the circuit simulation the electrical model of the clock line trace (wire). Perform the simulation with clock lines that have different physical lengths and widths to determine the constraints needed on the layout of your circuit to minimize ringing, rise and fall times and current supply levels.

• The exact values of the resistors and capacitors needed to reduce ringing will depend on your circuit application. Specifically, the length of the clock line, the number of circuits that your clock line drives and the current drive capacity of your clock driver circuits.

References

• University of Southern California: Optimizing the Energy-Delay-Ringing Product in On-Chip CMOS Line Drivers
• Fairchild Semiconductor; High-Speed-CMOS Designs Address Noise and I/0; Oct 1984
• RF Cafe: Pulse Definition
• Electronic Engineering Dictionary: Digital Pulse
• Patentgenius.com: Technique to Reduce Reflections and Ringing on CMOS Interconnections
• Fairchild Semiconductor; Transmission-Line Effects Influence High-Speed CMOS; Mar 1985