What Is a Vhdl With/Select Statement?
Hardware description languages are often used to describe functions that return only true or false, known as Boolean functions. In Very High Speed Integrated Circuit Hardware Description Language (VHDL), the select statement, which is similar to the switch and case statements in other languages, provides a convenient means of doing so.
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Syntax
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The general syntax of the with-select-when statement is:
with {selection} select
{expression} when {condition},
{expression} when {condition},
{expression} when {others}.
Evaluation
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When VHDL tools evaluate a with-select-when statement they check if the selecting expression is equal to any of the when conditions. The expression selected is the first with a matching condition. The condition can be a single value or a range of values.
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Limitations
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In a VHDL with-select-when statement, no two conditions can overlap and all possible values of {selection} must be covered by the set of conditions, unless an others condition is included. The others condition represents expression values that are not otherwise represented.
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